(1) Field of the Invention
The present invention relates to solid-state imaging devices and manufacturing methods of the same and, in particular to a solid-state imaging device that includes a read transistor for reading signal charges accumulated in a signal accumulation region.
(2) Description of the Related Art
In the field of solid-state imaging devices, a large number of techniques have been proposed which relate to a structure of an amplifying solid-state imaging device (metal-oxide semiconductor (MOS) image sensor) (see, for example, Patent Reference 1: Japanese Unexamined Patent Application Publication No. 2006-324482). The amplifying solid-state imaging device has an advantage in that power consumption is lower than that of a charge coupled device (CCD) image sensor. Further, the amplifying solid-state imaging device has an advantage in that a sensor and a peripheral circuit can be easily integrated since the sensor and the peripheral circuit can be manufactured through the same complementary metal oxide semiconductor (CMOS) process.
A conventional solid-state imaging device disclosed in Patent Reference 1 will be described below.
FIG. 1 to FIG. 3 are diagrams which illustrate a structure of the conventional solid-state imaging device disclosed in Patent Reference 1. FIG. 1 is a top plan view which illustrates a structure of a photoelectric conversion unit and a signal read unit for a single pixel. FIG. 2 is a cross sectional view which illustrates a structure of the solid-state imaging device taken along the line Y1-Y2 of FIG. 1. FIG. 3 is a cross sectional view which illustrates a structure of the solid-state imaging device taken along the line X1-X2 of FIG. 1
As illustrated in FIG. 1 to FIG. 3, each of pixels is formed in a P well 101. Each pixel includes: a signal accumulation region (photodiode) 102; a gate oxide film 103; a gate electrode 104; a drain region 105; a surface shield layer 106; an isolation region 107; a defect suppression layer 108; and a capacity enlargement region 112.
The signal accumulation region 102 is an N-type diffusion layer formed in the P well 101. The signal accumulation region 102 is a photoelectric conversion unit that converts light into signal charges and accumulates the converted signal charges.
The gate electrode 104 is formed adjacent to the signal accumulation region 102 above the P well 101 with the gate oxide film 103 being disposed therebetween.
The signal accumulation region 102, the gate electrode 104, and the drain region 105 are included in a single MOS transistor (read transistor). The MOS transistor is included in a signal read unit that reads signal charges accumulated in the signal accumulation region 102.
The surface shield layer 106 is a P-type diffusion layer. The surface shield layer 106 is located above the signal accumulation region 102 and formed on a surface of the P well 101.
The isolation region 107 is a shallow trench isolation (STI) made by etching a semiconductor substrate.
The defect suppression layer 108 is a P-type diffusion layer and formed adjacent to the side and bottom surfaces of the isolation region 107. The defect suppression layer 108 is a layer for suppressing a crystal defect resulting from forming the isolation region 107.
The capacity enlargement region 112 is formed between the defect suppression layer 108 and the signal accumulation region 102. The capacity enlargement region 112 has a higher N-type dopant concentration than the signal accumulation region 102.
According to the above-described structure, the solid-state imaging device disclosed in the Patent Reference 1 is capable of reducing the amount of decrease, resulting from forming the defect suppression layer 108, in an accumulation amount of signal charges in the signal accumulation region 102, by including the capacity enlargement region 112.
With the solid-state imaging device disclosed in Patent Reference 1, however, when a width of the gate electrode 104 is shortened as a result of miniaturization, a width of a channel that transfers a signal (electron) from the signal accumulation region 102 to the drain region 105 is shortened. This poses a problem that an effective channel width becomes significantly shortened due to the defect suppression layer 108.
A detailed description on the above problem will be given with reference to FIG. 4.
FIG. 4A to FIG. 4F are diagrams which illustrate a dopant concentration distribution along the line X3-X4 of FIG. 3. FIG. 4A and FIG. 4B are diagrams which illustrate an N-type dopant concentration distribution. FIG. 4C and FIG. 4D are diagrams which illustrate a P-type dopant concentration distribution. FIG. 4E and FIG. 4F are diagrams which illustrate all dopant concentration distribution including the N-type and the P-type. Further, FIG. 4B, 4D, and FIG. 4F are diagrams which illustrate dopant concentration distribution in the case where a distance between X3 and X4 becomes shorter than that of FIG. 4A, 4C, and FIG. 4E due to a smaller pixel size resulting from miniaturization.
As illustrated in FIG. 4A and FIG. 4B, the N-type dopant concentration is constant regardless of the position along the line X3-X4. On the other hand, as illustrated in FIG. 4C and FIG. 4D, the P-type dopant concentration becomes higher near the defect suppression layer 108 compared to that under the center of the gate electrode 104, and becomes lower as becomes more distant from the defect suppression layer 108. This is attributed to forming the defect suppression layer 108 that has a high P-type dopant concentration.
FIG. 5 is a conceptual diagram which illustrates an ion implantation of the P-type dopant that forms the 108. As illustrated in FIG. 5, the ion implantation is carried out using a resist 109, from a side surface of a trench in which the isolation region 107 is formed. At this time, the ion implantation is carried out so that the P-type dopant concentration peaks around the side surface of the isolation region 107 that includes lots of defects. Accordingly, the P-type dopant concentration peaks around the positions X3 and X4 on the side surface of the isolation region 107.
Thus, as illustrated in FIG. 4E and FIG. 4F, the all dopant concentration including both of the P-type and the N-type becomes higher near the defect suppression layer 108 compared to that under the center of the gate electrode 104. This causes the effective channel width of the read transistor to decrease. In the case where a pixel size is reduced as a result of miniaturization, in particular, the effective channel width significantly decreases since the distance between X3 and X4 becomes shorter, as illustrated in FIG. 4F.
As a result, with the conventional solid-state imaging device, a signal (electron) cannot be completely transferred, in some cases, from the signal accumulation region 102 to the drain region 105. Accordingly, with the conventional solid-state imaging device, the number of remaining electrons; that is, the number of electrons that have not been transferred and left in the signal accumulation region 102 increases.